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v1.3: RV12 32/64 Bit RISC-V CPU - RC #1

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@sphardy sphardy released this 05 Feb 14:50
· 492 commits to master since this release
v1.3-rc1
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sphardy Paul H
GPG key ID: 25CEB9FE915DD620
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Summary

Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 6-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.

Changes

New Features

  • Full Support for Privileged Spec v1.10 and User Spec v 2.2
  • Higher performance 6 stage pipeline

Release Notes

  • Documentation partially updated (missing CSR update info)
  • Physical Memory Protection Block not yet included

Bug Fixes

Below is a summary of key issues addressed. See GitHub Release Milestone for a full list & details.

  • Fixed: #18 - Core simulation issue in VCS
  • Fixed: #19 - Reading MCYCLE causes trap

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