Visual datapath upgrade

src/agent.rs

@@ -58,12 +58,13 @@ pub async fn emulation_core_agent(scope: ReactorScope<Command, DatapathUpdate>)
                     DatapathUpdate::MIPS(MipsStateUpdate::UpdateRegisters(datapath.registers));
                 let memory_update =
                     DatapathUpdate::MIPS(MipsStateUpdate::UpdateMemory(datapath.memory.clone()));
-                let stage_update =
-                    DatapathUpdate::MIPS(MipsStateUpdate::UpdateStage(datapath.current_stage));
+                let stage_update = DatapathUpdate::MIPS(MipsStateUpdate::UpdateStage(datapath.current_stage.clone()));
+                let coprocessor_update = DatapathUpdate::MIPS(MipsStateUpdate::UpdateCoprocessor(datapath.coprocessor.clone()));
                 state.scope.send(state_update).await.unwrap();
                 state.scope.send(register_update).await.unwrap();
                 state.scope.send(memory_update).await.unwrap();
                 state.scope.send(stage_update).await.unwrap();
+                state.scope.send(coprocessor_update).await.unwrap();
             }
         }
     }

src/agent/datapath_reducer.rs

@@ -1,6 +1,7 @@
 use crate::agent::messages::MipsStateUpdate;
 use crate::emulation_core::architectures::AvailableDatapaths::MIPS;
 use crate::emulation_core::architectures::{AvailableDatapaths, DatapathUpdate};
+use crate::emulation_core::mips::coprocessor::MipsFpCoprocessor;
 use crate::emulation_core::mips::datapath::{DatapathState, Stage};
 use crate::emulation_core::mips::memory::Memory;
 use crate::emulation_core::mips::registers::GpRegisters;
@@ -19,6 +20,7 @@ pub struct MipsCoreState {
     pub registers: GpRegisters,
     pub memory: Memory,
     pub current_stage: Stage,
+    pub coprocessor: MipsFpCoprocessor
 }
 
 impl Default for DatapathReducer {
@@ -42,25 +44,36 @@ impl Reducible for DatapathReducer {
                         state,
                         registers: self.mips.registers,
                         memory: self.mips.memory.clone(),
-                        current_stage: self.mips.current_stage,
+                        current_stage: self.mips.current_stage.clone(),
+                        coprocessor: self.mips.coprocessor.clone(),
                     },
                     MipsStateUpdate::UpdateRegisters(registers) => MipsCoreState {
                         state: self.mips.state.clone(),
                         registers,
                         memory: self.mips.memory.clone(),
-                        current_stage: self.mips.current_stage,
+                        current_stage: self.mips.current_stage.clone(),
+                        coprocessor: self.mips.coprocessor.clone(),
                     },
                     MipsStateUpdate::UpdateMemory(memory) => MipsCoreState {
                         state: self.mips.state.clone(),
                         registers: self.mips.registers,
                         memory,
-                        current_stage: self.mips.current_stage,
+                        current_stage: self.mips.current_stage.clone(),
+                        coprocessor: self.mips.coprocessor.clone(),
                     },
                     MipsStateUpdate::UpdateStage(stage) => MipsCoreState {
                         state: self.mips.state.clone(),
                         registers: self.mips.registers,
                         memory: self.mips.memory.clone(),
                         current_stage: stage,
+                        coprocessor: self.mips.coprocessor.clone(),
+                    },
+                    MipsStateUpdate::UpdateCoprocessor(coprocessor) => MipsCoreState {
+                        state: self.mips.state.clone(),
+                        registers: self.mips.registers,
+                        memory: self.mips.memory.clone(),
+                        current_stage: self.mips.current_stage.clone(),
+                        coprocessor
                     },
                 },
             },

src/agent/messages.rs

@@ -1,7 +1,8 @@
+use crate::emulation_core::mips::coprocessor::MipsFpCoprocessor;
+use crate::emulation_core::{architectures::AvailableDatapaths, mips::datapath::Stage};
 use crate::emulation_core::mips::datapath::DatapathState;
 use crate::emulation_core::mips::memory::Memory;
 use crate::emulation_core::mips::registers::GpRegisters;
-use crate::emulation_core::{architectures::AvailableDatapaths, mips::datapath::Stage};
 use serde::{Deserialize, Serialize};
 
 /// Commands sent from the UI thread to the worker thread.
@@ -26,4 +27,5 @@ pub enum MipsStateUpdate {
     UpdateRegisters(GpRegisters),
     UpdateMemory(Memory),
     UpdateStage(Stage),
+    UpdateCoprocessor(MipsFpCoprocessor),
 }

src/bin/main.rs

@@ -522,7 +522,7 @@ fn app(props: &AppProps) -> Html {
                     </div>
 
                     // Console
-                    <Footer parsermsg={(*parser_text_output).clone()} datapath={(*datapath.borrow()).clone()} memory_text_model={memory_text_model} memory_curr_instr={memory_curr_instr.clone()} active_tab={console_active_tab.clone()} communicator={props.communicator} show_input={show_input.clone()} command={command.clone()}/>
+                    <Footer parsermsg={(*parser_text_output).clone()} datapath_state={datapath_state.clone()} memory_text_model={memory_text_model} memory_curr_instr={memory_curr_instr.clone()} active_tab={console_active_tab.clone()} communicator={props.communicator} show_input={show_input.clone()} command={command.clone()}/>
                 </div>
 
                 // Right column

src/emulation_core/mips/control_signals.rs

@@ -278,9 +278,10 @@ pub enum RegWrite {
 }
 
 pub mod floating_point {
+    use serde::{Deserialize, Serialize};
     use super::super::constants::*;
 
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub struct FpuControlSignals {
         pub cc: Cc,
         pub cc_write: CcWrite,
@@ -300,7 +301,7 @@ pub mod floating_point {
     ///
     /// For the sake of this project, it will usually be assumed that this will
     /// be 0, however the functionality is available to be extended.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum Cc {
         /// Use condition code register 0. Default in most operations. Can be
         /// additionally used in the case where the condition code register is
@@ -310,7 +311,7 @@ pub mod floating_point {
     }
 
     /// Determines if the condition code register file should be written to.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum CcWrite {
         #[default]
         NoWrite = 0,
@@ -321,7 +322,7 @@ pub mod floating_point {
     ///
     /// This is a special intermediary register that facilitates passing data between
     /// the main processing unit and the floating-point unit.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum DataSrc {
         /// Use data from the main processing unit. Specifically, the data from register
         /// `rt` from a given instruction. This value can additionally be used in the cases
@@ -342,7 +343,7 @@ pub mod floating_point {
     /// For the latter two functions, it is imperative to unset the [`RegWrite`](super::RegWrite) and
     /// [`FpuRegWrite`] control signals in cases where registers should not be modified
     /// with unintended data.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum DataWrite {
         /// - Do not write to the data register.
         /// - Source data to write to the main processing unit register file from the main
@@ -373,7 +374,7 @@ pub mod floating_point {
     ///
     /// *Implementation note:* The bits set for the comparator are intended to match
     /// the bits used in the `cond` field of a `c.cond.fmt` instruction.
-    #[derive(Clone, Debug, Default, PartialEq)]
+    #[derive(Clone, Debug, Default, PartialEq, Serialize, Deserialize)]
     pub enum FpuAluOp {
         #[default]
         /// `_0000` (0):
@@ -437,7 +438,7 @@ pub mod floating_point {
     ///
     /// This directly overrides any branch decisions decided by the main processing unit.
     /// The [`Branch`](super::Branch) control signal should not be set in addition to this signal.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuBranch {
         /// Do not consider branching.
         #[default]
@@ -451,7 +452,7 @@ pub mod floating_point {
     /// register's new data will be.
     ///
     /// This decision, if set, overrides the decision from the [`DataWrite`] control signal.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuMemToReg {
         /// Do not use data from memory. Use the result of the [`DataWrite`] control signal.
         #[default]
@@ -463,7 +464,7 @@ pub mod floating_point {
 
     /// Determines, given that [`FpuRegWrite`] is set, which destination register to write
     /// to, which largely depends on the instruction format.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuRegDst {
         /// Use register `ft`.
         Reg1 = 0,
@@ -480,7 +481,7 @@ pub mod floating_point {
     ///
     /// While all buses carrying information are 64-bits wide, some bits of the bus may be
     /// ignored in the case of this control signal.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuRegWidth {
         /// Use words (32 bits). Equivalent to a single-precision floating-point value.
         Word = 0,
@@ -503,7 +504,7 @@ pub mod floating_point {
     }
 
     /// Determines if the floating-point register file should be written to.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuRegWrite {
         /// Do not write to the floating-point register file.
         #[default]
@@ -517,7 +518,7 @@ pub mod floating_point {
     /// to follow through with a branch.
     ///
     /// This signal is what is sent to the main processor.
-    #[derive(Clone, Default, PartialEq)]
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuTakeBranch {
         #[default]
         NoBranch = 0,

src/emulation_core/mips/coprocessor.rs

@@ -1,5 +1,6 @@
 //! Implementation of a MIPS64 floating-point coprocessor.
 
+use serde::{Deserialize, Serialize};
 use super::constants::*;
 use super::control_signals::floating_point::*;
 use super::instruction::Instruction;
@@ -8,7 +9,7 @@ use super::instruction::Instruction;
 ///
 /// Different from the main processor, much of the functionality of the coprocessor
 /// is controlled remotely using its available API calls.
-#[derive(Clone, Default, PartialEq)]
+#[derive(Clone, Default, PartialEq, Serialize, Debug, Deserialize)]
 pub struct MipsFpCoprocessor {
     instruction: Instruction,
     pub signals: FpuControlSignals,
@@ -20,7 +21,7 @@ pub struct MipsFpCoprocessor {
     pub data: u64,
 }
 
-#[derive(Clone, Default, PartialEq)]
+#[derive(Clone, Default, PartialEq, Debug, Serialize, Deserialize)]
 pub struct FpuState {
     pub instruction: u32,
     pub op: u32,

src/emulation_core/mips/instruction.rs

@@ -1,5 +1,6 @@
 //! Abstract representation of an instruction.
 
+use serde::{Deserialize, Serialize};
 use crate::parser::parser_structs_and_enums::GP_REGISTERS;
 
 use super::constants::*;
@@ -24,7 +25,7 @@ use super::constants::*;
 ///   determining the type of instruction executed (in `mul`, `dmul`, `dmulu`, `div`, `ddiv`,
 ///   `ddivu`), or be used as a "hint" field for certain instructions (of note are `jr` and `jalr`).
 /// - function: Secondary field for determining the type of instruction executed.
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct RType {
     pub op: u8,
     pub rs: u8,
@@ -34,15 +35,15 @@ pub struct RType {
     pub funct: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct IType {
     pub op: u8,
     pub rs: u8,
     pub rt: u8,
     pub immediate: u16,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct JType {
     pub op: u8,
     pub addr: u32,
@@ -62,14 +63,14 @@ pub struct JType {
 /// - opcode: SPECIAL (`000000`)
 /// - code: Available for use as software parameters.
 /// - funct: SYSCALL (`001100`)
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct SyscallType {
     pub op: u8,
     pub code: u32,
     pub funct: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct FpuRType {
     pub op: u8,
     pub fmt: u8,
@@ -79,7 +80,7 @@ pub struct FpuRType {
     pub function: u8,
 }
 
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
 pub struct FpuIType {
     pub op: u8,
     pub base: u8,
@@ -105,15 +106,15 @@ pub struct FpuIType {
 /// - sub: Operation subcode field for COP1 register immediate-mode instructions.
 /// - rt: CPU register - can be either source or destination.
 /// - fs: FPU register - can be either source or destination.
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
 pub struct FpuRegImmType {
     pub op: u8,
     pub sub: u8,
     pub rt: u8,
     pub fs: u8,
 }
 
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
 pub struct FpuCompareType {
     pub op: u8,
     pub fmt: u8,
@@ -142,7 +143,7 @@ pub struct FpuCompareType {
 /// - nd: Nullify delay. If set, the branch is Likely, and the delay slot instruction is not executed. (Not necessary for this project.)
 /// - tf: True/False. The type of condition for a comparison.
 /// - offset: Signed offset field used in address calculations.
-#[derive(Clone, Copy, Debug, PartialEq)]
+#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
 pub struct FpuBranchType {
     pub op: u8,
     pub bcc1: u8,
@@ -152,7 +153,7 @@ pub struct FpuBranchType {
     pub offset: u16,
 }
 
-#[derive(Clone, Debug, PartialEq)]
+#[derive(Clone, Debug, PartialEq, Serialize, Deserialize)]
 pub enum Instruction {
     RType(RType),
     IType(IType),