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v2.4.3

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@laborleben laborleben released this 25 May 13:33
· 676 commits to master since this release

ENH: Mimosa26 support
ENH: simultaneous trigger timestamp and ID for TLU module
BUG: enhance signal delay in TDC for inverted signals
ENH: JTAG support
ENH: Keithley switcher card support
ENH: Arduino support
ENH: Suess prober support
ENH: adding trigger threshold for TLU module
BUG: SiTcp corrupted large slow commands
ENH: adding TDC testbench
BUG: fixed writing HL register twice when using lazy style and RL register
BUG: fix duty cycle and phase shift in DCM_sim module
ENH: adding is_initialized property for all basil classes

... and again lots of cleaning up and minor improvements.