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Add AXIS Cache IP, FPGA code housekeeping, etc. #826

Merged
merged 15 commits into from
Jan 24, 2025
Merged

Add AXIS Cache IP, FPGA code housekeeping, etc. #826

merged 15 commits into from
Jan 24, 2025

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n-eiling
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@n-eiling n-eiling commented Oct 27, 2024 •
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  • Various fixes for FPGA use cases.
  • New IP driver axis_cache
  • cleans up config files
  • improves comments

I modified the cast hook so it also works for writes. I use this for the DPsim VILLASnode interface to convert between double and complex.

@n-eiling n-eiling marked this pull request as ready for review November 4, 2024 14:37
@n-eiling n-eiling requested a review from stv0g as a code owner November 4, 2024 14:37
@n-eiling n-eiling changed the title Improving FPGA communication Add AXIS Cache IP, FPGA code housekeeping, etc. Nov 4, 2024
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stv0g previously requested changes Nov 4, 2024
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stv0g commented Nov 5, 2024

Thanks for addressing the nits about the code-style. Unfortunately, I think the DCO check isnt happy anymore about it..

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n-eiling commented Nov 5, 2024

i used the wrong mail address in the github ui. didn't know this affects the DCO check :)

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Let's merge this and move the discussion to VILLASframework/documentation#89

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n-eiling commented Jan 7, 2025

@stv0g ping

@n-eiling
fpga: Add driver for new register interface of axis cache IP
a1f265a 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: Add new Dino configuration register that allows triggering the …
e544bce 
…DAC before the time step to dino.cpp

Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: Add axis_cache.cpp to CMakeLists.txt
24b582c 
Signed-off-by: Niklas Eiling <[email protected]>
@n-eiling
fpga: Fix I2c causing an error when Dino FMC is not connected. We loo…
0990c16 
…se the self check, but this is not really possible if there is no Dino FMC.

Signed-off-by: Niklas Eiling <[email protected]>
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ping again.

@n-eiling n-eiling merged commit 16b6a21 into master Jan 24, 2025
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@n-eiling n-eiling deleted the dino-dev branch January 24, 2025 09:32
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