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SPI Engine: SDO data prefetch #1501
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SDO data can now be clocked in independently from the offload trigger. This allows lower latencies for executing transfers, since the data can be obtained from the DMA before the trigger. It also better separates the command path from the data path. SDO data source behavior is altered: previously, with SDO_STREAMING=1 the SPI Engine would prioritize the SDO memory and switch to AXI Streaming when empty. This unused automatic switching is now removed: if the SPI Engine is built with SDO_STREAMING=1 it will only get SDO data from AXI Streaming, and with SDO_STREAMING=0 it will only use the SDO memory. Signed-off-by: Laez Barbosa <[email protected]>
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changed it so the SDO data source is a parameter (synthesis-time), rebased on main |
Tested on AD4052 with cora, same behavior as in main |
ad4052_ardz.de10nano jenkins build fails with this error |
Signed-off-by: Laez Barbosa <[email protected]>
Signed-off-by: Laez Barbosa <[email protected]>
Signed-off-by: sarpadi <[email protected]>
@@ -322,6 +304,18 @@ module spi_engine_offload #( | |||
end | |||
end | |||
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always @(posedge spi_clk ) begin |
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always @(posedge spi_clk ) begin | |
always @(posedge spi_clk) begin |
@@ -13,3 +13,5 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_ | |||
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 | |||
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sysid_gen_sys_init_file | |||
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set_property strategy Performance_Retiming [get_runs impl_1] |
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This usually goes in the system_project.tcl not _db (28 _project.tcl vs 2 _bd.tcl)
@@ -95,7 +95,7 @@ module spi_engine_offload #( | |||
localparam SDO_SOURCE_MEM = 1'b0; | |||
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reg spi_active = 1'b0; | |||
reg sdo_source_select = SDO_SOURCE_MEM; | |||
wire sdo_source_select; |
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Move to wires section of file?
@@ -111,10 +111,12 @@ module spi_engine_offload #( | |||
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next; | |||
wire spi_enable; | |||
wire trigger_posedge; | |||
reg sdo_mem_valid; |
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Move to reg section of file?
PR Description
Allows spi_engine_execution get sdo data independently of the instruction command. This reduces the trigger to transfer latency, and opens the door to further pipelining this path or reducing latency even more.
(this PR should be merged after #1499)
PR Type
PR Checklist