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SPI Engine: SDO data prefetch #1501

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SPI Engine: SDO data prefetch #1501

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d845ac3
SPI Engine: decouple SDO data handshake from control
LBFFilho Sep 6, 2024
c504d82
projects/ad4052/de10nano: update required quartus version
LBFFilho Jan 17, 2025
a87a4c6
Update license headers for 2025
LBFFilho Jan 17, 2025
61558f3
ad4052/cora: Update impl strategy for timing closure
sarpadi Jan 21, 2025
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6 changes: 3 additions & 3 deletions docs/regmap/adi_regmap_spi_engine.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ ENDTITLE
REG
0x00
VERSION
Version of the peripheral. Follows semantic versioning. Current version 1.03.01.
Version of the peripheral. Follows semantic versioning. Current version 1.04.00.
ENDREG

FIELD
Expand All @@ -19,13 +19,13 @@ RO
ENDFIELD

FIELD
[15:8] 0x00000003
[15:8] 0x00000004
VERSION_MINOR
RO
ENDFIELD

FIELD
[7:0] 0x00000001
[7:0] 0x00000000
VERSION_PATCH
RO
ENDFIELD
Expand Down
4 changes: 2 additions & 2 deletions library/spi_engine/axi_spi_engine/axi_spi_engine.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -133,7 +133,7 @@ module axi_spi_engine #(
input [7:0] offload_sync_data
);

localparam PCORE_VERSION = 'h010301;
localparam PCORE_VERSION = 'h010400;
localparam S_AXI = 0;
localparam UP_FIFO = 1;

Expand Down
24 changes: 11 additions & 13 deletions library/spi_engine/spi_engine_execution/spi_engine_execution.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -132,6 +132,8 @@ module spi_engine_execution #(

reg sdo_enabled = 1'b0;
reg sdi_enabled = 1'b0;
wire sdo_enabled_io;
wire sdi_enabled_io;

wire sdo_int_s;

Expand Down Expand Up @@ -165,7 +167,7 @@ module spi_engine_execution #(

wire end_of_sdi_latch;

wire sample_sdo;
wire sdo_io_ready;

(* direct_enable = "yes" *) wire cs_gen;

Expand Down Expand Up @@ -194,7 +196,6 @@ module spi_engine_execution #(
.sdo_idle_state(sdo_idle_state),
.left_aligned(left_aligned),
.word_length(word_length),
.sample_sdo(sample_sdo),
.sdo_io_ready(sdo_io_ready),
.transfer_active(transfer_active),
.trigger_tx(trigger_tx),
Expand All @@ -203,8 +204,6 @@ module spi_engine_execution #(
.cs_activate(cs_activate),
.end_of_sdi_latch(end_of_sdi_latch));

assign sample_sdo = sdo_data_valid && ((trigger_tx && last_bit) || (wait_for_io || exec_transfer_cmd));

assign cs_gen = inst_d1 == CMD_CHIPSELECT
&& ((cs_sleep_counter_compare == 1'b1) || cs_sleep_early_exit)
&& (cs_sleep_repeat == 1'b0)
Expand All @@ -217,6 +216,8 @@ module spi_engine_execution #(
sdi_enabled <= cmd[9];
end
end
assign sdo_enabled_io = (exec_transfer_cmd) ? cmd[8] : sdo_enabled;
assign sdi_enabled_io = (exec_transfer_cmd) ? cmd[9] : sdi_enabled;

always @(posedge clk) begin
if (cmd_ready & cmd_valid)
Expand Down Expand Up @@ -388,9 +389,9 @@ module spi_engine_execution #(
assign sync = cmd_d1[7:0];

assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_io_ready == 1'b1);
(sdo_enabled_io == 1'b0 || sdo_io_ready == 1'b1);
assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
(sdo_enabled_io == 1'b0 || last_transfer == 1'b1 || sdo_io_ready == 1'b1);

always @(posedge clk) begin
if (idle == 1'b1) begin
Expand All @@ -409,14 +410,11 @@ module spi_engine_execution #(
wait_for_io <= 1'b0;
end else begin
if (exec_transfer_cmd == 1'b1) begin
wait_for_io <= 1'b1;
transfer_active <= 1'b0;
wait_for_io <= !io_ready1;
transfer_active <= io_ready1;
end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
wait_for_io <= 1'b0;
if (last_transfer == 1'b0)
transfer_active <= 1'b1;
else
transfer_active <= 1'b0;
transfer_active <= !last_transfer;
end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
if (last_transfer == 1'b1 || io_ready2 == 1'b0)
transfer_active <= 1'b0;
Expand Down
48 changes: 23 additions & 25 deletions library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -55,7 +55,7 @@ module spi_engine_execution_shiftreg #(
// spi data
input [(DATA_WIDTH-1):0] sdo_data,
input sdo_data_valid,
output reg sdo_data_ready,
output sdo_data_ready,

output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
output reg sdi_data_valid,
Expand All @@ -70,8 +70,7 @@ module spi_engine_execution_shiftreg #(
input [ 7:0] word_length,

// timing from main fsm
input sample_sdo,
output reg sdo_io_ready,
output sdo_io_ready,
input transfer_active,
input trigger_tx,
input trigger_rx,
Expand All @@ -83,36 +82,35 @@ module spi_engine_execution_shiftreg #(
reg [ 7:0] sdi_counter = 8'b0;
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
reg [ SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
reg [(DATA_WIDTH-1):0] aligned_sdo_data, sdo_data_d;

wire trigger_rx_s;
wire [2:0] current_instr = current_cmd[14:12];
wire last_sdi_bit;

always @(posedge clk) begin
reg [(DATA_WIDTH-1):0] aligned_sdo_data, sdo_data_reg;
reg data_sdo_v;
wire sdo_toshiftreg;
wire last_sdi_bit;
wire trigger_rx_s;
wire [2:0] current_instr = current_cmd[14:12];

// sdo data handshake
assign sdo_data_ready = (!data_sdo_v) || sdo_toshiftreg;
assign sdo_io_ready = data_sdo_v;
always @(posedge clk ) begin
if (resetn == 1'b0) begin
sdo_data_ready <= 1'b0;
end else if (sdo_toshiftreg) begin
sdo_data_ready <= 1'b1;
end else if (sdo_data_valid == 1'b1) begin
sdo_data_ready <= 1'b0;
data_sdo_v <= 1'b0;
end else begin
if (sdo_data_ready && sdo_data_valid) begin
data_sdo_v <= 1'b1;
sdo_data_reg <= sdo_data;
end else if (sdo_toshiftreg) begin
data_sdo_v <= 1'b0;
end
end
end

// pipelined shifter for sdo_data
always @(posedge clk ) begin
if (resetn == 1'b0) begin
aligned_sdo_data <= 0;
sdo_io_ready <= 1'b0;
end else begin
if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
sdo_io_ready <= 1'b0;
end
if (sample_sdo) begin
sdo_data_d <= sdo_data;
sdo_io_ready <= 1'b1;
end
aligned_sdo_data <= sdo_data_d << left_aligned;
aligned_sdo_data <= sdo_data_reg << left_aligned;
end
end

Expand Down
42 changes: 18 additions & 24 deletions library/spi_engine/spi_engine_offload/spi_engine_offload.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -95,7 +95,7 @@ module spi_engine_offload #(
localparam SDO_SOURCE_MEM = 1'b0;

reg spi_active = 1'b0;
reg sdo_source_select = SDO_SOURCE_MEM;
wire sdo_source_select;
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Move to wires section of file?


reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
Expand All @@ -111,10 +111,12 @@ module spi_engine_offload #(
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
wire spi_enable;
wire trigger_posedge;
reg sdo_mem_valid;
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Move to reg section of file?


assign sdo_source_select = SDO_STREAMING;
assign cmd_valid = spi_active;
assign sdo_data_valid = (sdo_source_select == SDO_SOURCE_STREAM) ?
s_axis_sdo_valid : spi_active;
s_axis_sdo_valid : (spi_active && sdo_mem_valid);
assign s_axis_sdo_ready = (sdo_source_select == SDO_SOURCE_STREAM) ?
sdo_data_ready : 1'b0;
assign offload_sdi_valid = sdi_data_valid;
Expand Down Expand Up @@ -278,34 +280,14 @@ module spi_engine_offload #(
if (!spi_active) begin
// start offload when we have a valid trigger, offload is enabled and
// the DMA is enabled
if (trigger_posedge && spi_enable && (offload_sdi_ready || (SDO_STREAMING && s_axis_sdo_valid)))
if (trigger_posedge && spi_enable)
spi_active <= 1'b1;
end else if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
spi_active <= 1'b0;
end
end
end

always @(posedge spi_clk ) begin
if (!spi_resetn) begin
sdo_source_select <= SDO_SOURCE_MEM;
end else begin
if (SDO_STREAMING) begin
if (sdo_source_select == SDO_SOURCE_MEM) begin
// switch to streaming sdo after we're done with reading the sdo memory
if (sdo_data_valid && sdo_data_ready && (spi_sdo_rd_addr+1 == ctrl_sdo_wr_addr)|| (ctrl_sdo_wr_addr==0 && spi_active) ) begin
sdo_source_select <= SDO_SOURCE_STREAM;
end
end else begin
// switch back to sdo memory after last command accepted
if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
sdo_source_select <= SDO_SOURCE_MEM;
end
end
end
end
end

always @(posedge spi_clk) begin
if (!cmd_valid) begin
spi_cmd_rd_addr <= 'h00;
Expand All @@ -322,6 +304,18 @@ module spi_engine_offload #(
end
end

always @(posedge spi_clk ) begin
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Suggested change
always @(posedge spi_clk ) begin
always @(posedge spi_clk) begin

if (!spi_resetn) begin
sdo_mem_valid <= 1'b0;
end else begin
if (!spi_active && trigger_posedge && spi_enable) begin
sdo_mem_valid <= (ctrl_sdo_wr_addr != 'h00); // if ctrl_sdo_wr_addr is 0, mem is empty
end else if (sdo_data_ready && spi_active && sdo_mem_valid && (spi_sdo_rd_addr + 1'b1 == ctrl_sdo_wr_addr)) begin
sdo_mem_valid <= 1'b0;
end
end
end

always @(posedge ctrl_clk) begin
if (ctrl_mem_reset)
ctrl_cmd_wr_addr <= 'h00;
Expand Down
2 changes: 2 additions & 0 deletions projects/ad4052_ardz/coraz7s/system_bd.tcl
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Expand Up @@ -13,3 +13,5 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9

sysid_gen_sys_init_file

set_property strategy Performance_Retiming [get_runs impl_1]
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This usually goes in the system_project.tcl not _db (28 _project.tcl vs 2 _bd.tcl)

4 changes: 2 additions & 2 deletions projects/ad4052_ardz/de10nano/system_project.tcl
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@@ -1,9 +1,9 @@
###############################################################################
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

set REQUIRED_QUARTUS_VERSION 22.1std.0
set REQUIRED_QUARTUS_VERSION 23.1std.1
set QUARTUS_PRO_ISUSED 0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_project_intel.tcl
Expand Down
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