Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

WIP: Added amomin, amomax, amominu, amomaxu to Core & Caches #615

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

WIP: Added amomin, amomax, amominu, amomaxu to Core & Caches #615

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
231ce84
WIP: Added amomin, amomax, amominu, amomaxu to Core & Caches
drichmond Jan 6, 2022
469bf09
Added missing unique case statements
drichmond Jan 17, 2022
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions testbenches/common/v/vcache_profiler.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,10 @@ module vcache_profiler
wire inc_amoswap = inc_atomic & (decode_v_r.amo_subop == e_cache_amo_swap); // atomic swap
wire inc_amoor = inc_atomic & (decode_v_r.amo_subop == e_cache_amo_or); // atomic or
wire inc_amoadd = inc_atomic & (decode_v_r.amo_subop == e_cache_amo_add); // atomic add
wire inc_amomin = inc_atomic & (decode_v_r.amo_subop == e_cache_amo_min); // atomic min
wire inc_amomax = inc_atomic & (decode_v_r.amo_subop == e_cache_amo_max); // atomic max
wire inc_amominu = inc_atomic & (decode_v_r.amo_subop == e_cache_amo_minu); // atomic minu
wire inc_amomaxu = inc_atomic & (decode_v_r.amo_subop == e_cache_amo_maxu); // atomic maxu

wire inc_miss_ld = v_o & yumi_i & decode_v_r.ld_op & miss_v; // miss on load
wire inc_miss_st = v_o & yumi_i & decode_v_r.st_op & miss_v; // miss on store
Expand Down
2 changes: 1 addition & 1 deletion v/bsg_manycore_link_to_cache.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -157,7 +157,7 @@ module bsg_manycore_link_to_cache
e_cache_op: begin
return_pkt_type = e_return_credit;
end
e_remote_amoswap, e_remote_amoor, e_remote_amoadd: begin
e_remote_amoswap, e_remote_amoor, e_remote_amoadd, e_remote_amomin, e_remote_amomax, e_remote_amominu, e_remote_amomaxu: begin
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You also need to assign opcode in the case statement starting at line 285

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed

return_pkt_type = e_return_int_wb;
end
// should never happen
Expand Down
4 changes: 4 additions & 0 deletions v/bsg_manycore_tile_vcache.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,10 @@ module bsg_manycore_tile_vcache
, parameter vcache_amo_support_p = (1 << e_cache_amo_swap)
| (1 << e_cache_amo_or)
| (1 << e_cache_amo_add)
| (1 << e_cache_amo_min)
| (1 << e_cache_amo_minu)
| (1 << e_cache_amo_max)
| (1 << e_cache_amo_maxu)
)
(
input clk_i
Expand Down
5 changes: 5 additions & 0 deletions v/vanilla_bean/bsg_vanilla_defines.vh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -194,6 +194,11 @@
`define RV32_AMOOR_W {5'b01000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP}
`define RV32_AMOADD_W {5'b00000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP}

`define RV32_AMOMIN_W {5'b10000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP}
`define RV32_AMOMAX_W {5'b10100,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP}
`define RV32_AMOMINU_W {5'b11000,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP}
`define RV32_AMOMAXU_W {5'b11100,2'b??,5'b?????,5'b?????,3'b010,5'b?????,`RV32_AMO_OP}

// RV32F Instruction Encodings
`define RV32_OP_FP 7'b1010011
`define RV32_LOAD_FP 7'b0000111
Expand Down
6 changes: 5 additions & 1 deletion v/vanilla_bean/bsg_vanilla_pkg.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -47,10 +47,14 @@ typedef struct packed {

// remote request from vanilla core
//
typedef enum logic [1:0] {
typedef enum logic [2:0] {
e_vanilla_amoswap
, e_vanilla_amoor
, e_vanilla_amoadd
, e_vanilla_amomin
, e_vanilla_amomax
, e_vanilla_amominu
, e_vanilla_amomaxu
} bsg_vanilla_amo_type_e;

typedef struct packed
Expand Down
22 changes: 21 additions & 1 deletion v/vanilla_bean/cl_decode.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,11 @@ always_comb begin
// According the ISA, LR instruction don't read rs2
decode_o.read_rs2 = (instruction_i.funct7 ==? 7'b00001??) // amoswap
| (instruction_i.funct7 ==? 7'b01000??) // amoor
| (instruction_i.funct7 ==? 7'b00000??); // amoadd
| (instruction_i.funct7 ==? 7'b00000??) // amoadd
| (instruction_i.funct7 ==? 7'b10000??) // amomin
| (instruction_i.funct7 ==? 7'b10100??) // amomax
| (instruction_i.funct7 ==? 7'b11000??) // amominu
| (instruction_i.funct7 ==? 7'b11100??); // amomaxu
end
default: begin
decode_o.read_rs2 = 1'b0;
Expand Down Expand Up @@ -228,6 +232,22 @@ always_comb begin
decode_o.is_amo_op = 1'b1;
decode_o.amo_type = e_vanilla_amoadd;
end
`RV32_AMOMIN_W: begin
decode_o.is_amo_op = 1'b1;
decode_o.amo_type = e_vanilla_amomin;
end
`RV32_AMOMAX_W: begin
decode_o.is_amo_op = 1'b1;
decode_o.amo_type = e_vanilla_amomax;
end
`RV32_AMOMINU_W: begin
decode_o.is_amo_op = 1'b1;
decode_o.amo_type = e_vanilla_amominu;
end
`RV32_AMOMAXU_W: begin
decode_o.is_amo_op = 1'b1;
decode_o.amo_type = e_vanilla_amomaxu;
end
default: begin
decode_o.is_amo_op = 1'b0;
decode_o.amo_type = e_vanilla_amoswap;
Expand Down