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WIP: stm32 flash rework + ch32 flash rework and implementation #1642

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WIP: stm32 flash rework + ch32 flash rework and implementation #1642

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perigoso
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@perigoso perigoso commented Oct 5, 2023

Detailed description

This is the work I have been doing on the stm32 flash rework + ch32 flash implementation, for now deeply intertwined and built over #1399, it is in a very rough state, and this PR is just a draft, don't mind the vagueness and incompleteness

Your checklist for this pull request

  • I've read the Code of Conduct
  • I've read the guidelines for contributing to this repository
  • It builds for hardware native (make PROBE_HOST=native)
  • It builds as BMDA (make PROBE_HOST=hosted)
  • I've tested it to the best of my ability
  • My commit messages provide a useful short description of what the commits do

Closing issues

dragonmux and others added 30 commits October 3, 2023 16:33
@dragonmux @rg-silva
riscv_debug: Begun building a scan handler for RISC-V debug v0.13 dev…
cae7a9a 
…ices
@dragonmux @rg-silva
riscv_debug: Created a stub for initialising a DMI
c748c6a
@dragonmux @rg-silva
riscv_debug: Implemented a way to read/write the DTM control/status r…
9614e25 
…egister
@dragonmux @rg-silva
riscv_debug: Moved the JTAG-specific DTM handler into the JTAG DTM im…
65fc898 
…plementation file
@dragonmux @rg-silva
riscv_debug: Implemented support for reading and dispatching the DTM …
cc6e1b3 
…version
@dragonmux @rg-silva
riscv_debug: Implemented reference counting and stub structures for t…
b811004 
…he DMs and Harts
@dragonmux @rg-silva
riscv_debug: Restructed riscv_dmi_init() and riscv_jtag_dtm_init() to…
ec31117 
… prepare for scanning for DMs
@dragonmux @perigoso @rg-silva
riscv_debug: Handle the idle cycles component of the DTMCS register
a0d04ad 
Co-Authored-By: Rafael Silva <[email protected]>
@dragonmux @rg-silva
riscv_debug: Implemented a way to read the DMI address space
ef82b62
@dragonmux @rg-silva
riscv_debug: Implemented logic for iterating and discovering DMs
f441709
@dragonmux @rg-silva
riscv_debug: Begun implementing the hart enumeration process
322931c
@dragonmux @rg-silva
riscv_debug: Implemented enumeration of the harts associated with a DM
3d911d6
@dragonmux @rg-silva
riscv_debug: Implemented support for grabbing the hart's address bus …
9628555 
…width and system bus version
@dragonmux @rg-silva
riscv_debug: Implemented halt and resume support in preparation for r…
dbb7446 
…eading CSRs and memory from a hart
@dragonmux @rg-silva
riscv_debug: Implemented readout of CSRs and reading the 4 hart ident…
324ba8b 
…ification registers
@dragonmux @rg-silva
riscv_debug: Implemented readout of the ISA register to determine add…
741a865 
…ress width
@dragonmux @rg-silva
riscv_debug: Implemented the ability for riscv_reg_read() to do 128-,…
09d8c12 
… 64-, and 32-bit reads as required
@dragonmux @rg-silva
riscv_debug: Implemented support for discovering the target Hart's IS…
d0fe0b3 
…A and access width
@dragonmux @rg-silva
riscv_debug: Implemented writing to CSRs
8a980e8
@dragonmux @rg-silva
riscv_debug: Created probe stubs for probing RISC-V 32- and 64-bit ta…
3d29e9a 
…rgets
@dragonmux @rg-silva
riscv_debug: Set up the target designer code field
6175aa2
@dragonmux @rg-silva
riscv_debug: Documented the used CSR addresses
abda4b1
@dragonmux @rg-silva
riscv_debug: Implemented the ability to force a CSR access to a speci…
43f90a5 
…fic width
@dragonmux @rg-silva
riscv_debug: Implemented single-stepping support in riscv_halt_resume()
c44d053
@dragonmux @rg-silva
riscv_debug: Added definitions for the abstract memory access command
ee401eb
@dragonmux @rg-silva
riscv_debug: Implemented arbitrary memory read
6fc6d36
@dragonmux @rg-silva
riscv_debug: Fixed the target hart not being halted during probing
e7b81ca
@dragonmux @rg-silva
riscv_debug: Added some DEBUG_TARGET information to the CSR functions…
25d500f 
… and a failure warning to the CSR wait complete function
@dragonmux @rg-silva
riscv_debug: Implemented the target check_error hook
9f06826
@dragonmux @rg-silva
riscv_debug: Made more of the DM and hart machinary available in the …
1fca546 
…header
dragonmux and others added 29 commits October 3, 2023 16:44
@dragonmux @rg-silva
esp32c3: Implemented i-cache invalidation and reload for post-complet…
d14ed5c 
…ion of Flash operations
@dragonmux @rg-silva
esp32c3: Improved the setup for esp32c3_spu_run_command()
38ffd3e
@dragonmux @rg-silva
esp32c3: Refactored out the innards of esp32c3_spi_run_command() from…
9b6a041 
… esp32c3_spi_write()
@dragonmux @rg-silva
esp32c3: Improved our handling of chip select hold in esp32c3_spi_wri…
dc4925e 
…te()
@dragonmux @rg-silva
esp32c3: Cleaned up the handling of the SPI1 misc register in esp32c3…
8ebe4d3 
…_spi_read()
@dragonmux @rg-silva
esp32c3: Cleaned up and improved the data handling in esp32c3_spi_rea…
971bfaa 
…d() and esp32c3_spi_write()
@dragonmux @rg-silva
esp32c3: Hacky patch to make Flash write almost work correctly at the…
82af43f 
… loss of a huge amount of speed (25% the speed)
@dragonmux @rg-silva
esp32c3: Switched errors over to using DEBUG_ERROR instead of abusi…
fe722de 
…ng `DEBUG_WARN`
@perigoso @rg-silva
target/esp32c3: fix sfdp function signature
93b7ab6
@perigoso @rg-silva
hosted: barebones wch-link implementation
c0d6105
@perigoso @rg-silva
buffer_utils: Implemented a big endian 32-bit write
192dfe8
@perigoso @rg-silva
hosted/wchlink: implement DMI transfer
6ea9e73
@perigoso @rg-silva
riscv_debug: expose DMI operation and status defines
e5aa920
@perigoso @rg-silva
jep106: add BMD internal flag
5157ac5 
Used to mark codes that are not part of the JEP106 or any other standard
but are used internally by BMD to identify targets that don't provide a
usable identification codes
@perigoso @rg-silva
jep106: add internal WCH non-jep106 code
9882d33
@perigoso @rg-silva
riscv_jtag_dtm: move RV_DMI_TOO_SOON handling one level up
3a4e1c2
@perigoso @rg-silva
hosted/wchlink: implement RISC-V DTM handler
c769d53
@perigoso @rg-silva
command: add rvswd scan routine command
46c944d
@perigoso @rg-silva
hosted/wchlink: implement RVSWD scan
baaef78
@perigoso @rg-silva
riscv_debug: handle CH32V3x quirk
f376556 
The chip replies ok when probing the breakpoints but the reply is empty

Co-authored-by: mean <[email protected]>
@perigoso @rg-silva
riscv32: add ch32v3 target probe
0f4392a
@perigoso @rg-silva
!fixme! mass erase rework, drop after merge and rebase
fbca4ba
@perigoso @rg-silva
esp32c3: refactor with new mass erase target API
531b85b
@perigoso @rg-silva
ch32vx: implement electronic signature (ESIG) register handling
7e548c9
@perigoso @rg-silva
target/ch32f1: replace macros with functions
147ea81
@perigoso @rg-silva
target/ch32f1: longer variable naming
23e48eb
@perigoso @rg-silva
target/ch32f1: remove debug verify code
4d13cc3
@perigoso @rg-silva
target/ch32f1: const correctness
d357726
@perigoso @rg-silva
!fixme! stm32 flash
18e9f01
@dragonmux dragonmux added this to the v2.0 release milestone Oct 28, 2023
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@perigoso @dragonmux