Qt Interface

- qt interface added to send commands from computer
- gitignore added
- simulation source for tx
- ip chechksum calculation extended
- command length shortened from 2 to 1 bytes (256 commands should be enough)

.gitignore

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+ethernet_core.srcs/sources_1/ip/gig_ethernet_core/*
+ethernet_core.srcs/sources_1/ip/ila_0/*
+ethernet_core.srcs/sources_1/ip/ila_1/*
+ethernet_core/*
+*.user
+build-*

ethernet_core.srcs/sim_2/new/simul_tx.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09/28/2016 04:16:52 PM
+-- Design Name: 
+-- Module Name: simul - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity simul_tx is
+--  Port ( );
+end simul_tx;
+
+architecture Behavioral of simul_tx is
+component udp_tx
+Generic (   mac_dest    : std_logic_vector(47 downto 0) := x"ff_ff_ff_ff_ff_ff";
+            ip_src   : std_logic_vector(31 downto 0);
+            ip_dest   : std_logic_vector(31 downto 0)
+  );
+  Port (    userclk2    :   in std_logic;
+            gmii_txd    :   out std_logic_vector(7 downto 0);
+            gmii_tx_en  :   out std_logic;
+
+            ifdata      :   in std_logic; -- enablement of sending
+            data_length :   in std_logic_vector(15 downto 0);
+            data        :   in std_logic_vector(1023 downto 0)        
+  );
+end component;
+
+shared variable counter : integer := 0;
+constant clk125_period : time := 8 ns;
+signal data_int        :   std_logic_vector(1023 downto 0) := (others => '0');
+signal StartSending     : std_logic := '0';
+signal userclk2_int     : std_logic := '0';
+
+begin
+data_int(7 downto 0) <= x"aa";
+
+UUT: udp_tx generic map (
+      mac_dest      => x"ec_f4_bb_62_9f_b4",
+      --mac_dest      => x"ff_ff_ff_ff_ff_ff",
+      ip_src        => x"c0_a8_00_02",
+      ip_dest       => x"c0_a8_00_01"
+      )
+      port map (
+      userclk2      => userclk2_int,
+      gmii_txd      => open,
+      gmii_tx_en    => open,
+      ifdata        => StartSending,
+      data_length   => x"0001",
+      data          => data_int
+      );
+
+
+     clk125_process: process
+     begin
+         userclk2_int <= '1';
+         wait for clk125_period/2;
+         userclk2_int <= '0';
+         wait for clk125_period/2;
+      end process;
+
+      counter_process: process(userclk2_int)
+      begin
+        if rising_edge(userclk2_int) then
+            counter := counter + 1;
+            if counter = 500 then
+                counter := 0;
+                StartSending <= not StartSending;
+            end if;
+        end if;
+      end process;
+
+end Behavioral;

ethernet_core.srcs/sim_2/new/simul_tx_behav.wcfg

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+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="simul_tx_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="simul_tx" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="79040228900000fs"></ZoomStartTime>
+      <ZoomEndTime time="79040293900001fs"></ZoomEndTime>
+      <Cursor1Time time="79040288000000fs"></Cursor1Time>
+   </zoom_setting>
+   <WVObjectSize size="6" />
+   <wvobject type="array" fp_name="/simul_tx/data_int">
+      <obj_property name="ElementShortName">data_int[1023:0]</obj_property>
+      <obj_property name="ObjectShortName">data_int[1023:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/simul_tx/StartSending">
+      <obj_property name="ElementShortName">StartSending</obj_property>
+      <obj_property name="ObjectShortName">StartSending</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/simul_tx/userclk2_int">
+      <obj_property name="ElementShortName">userclk2_int</obj_property>
+      <obj_property name="ObjectShortName">userclk2_int</obj_property>
+   </wvobject>
+   <wvobject type="other" fp_name="/simul_tx/clk125_period">
+      <obj_property name="ElementShortName">clk125_period</obj_property>
+      <obj_property name="ObjectShortName">clk125_period</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/simul_tx/UUT/gmii_txd_int">
+      <obj_property name="ElementShortName">gmii_txd_int[7:0]</obj_property>
+      <obj_property name="ObjectShortName">gmii_txd_int[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/simul_tx/UUT/ip_checksum">
+      <obj_property name="ElementShortName">ip_checksum[31:0]</obj_property>
+      <obj_property name="ObjectShortName">ip_checksum[31:0]</obj_property>
+   </wvobject>
+</wave_config>