Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[dv] Avoid imports into class scope #26002

Open
wants to merge 2 commits into
base: master
Choose a base branch
from
Open

[dv] Avoid imports into class scope #26002

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
c9956b2
[rstmgr,dv] Move import in rstmgr_cnsty_chk class
rswarbrick Jan 24, 2025
3832d48
[uart,dv] Avoid importing into uart_env_cov
rswarbrick Jan 24, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 2 additions & 5 deletions hw/ip/uart/dv/env/uart_env_cov.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,20 +5,17 @@
class uart_env_cov extends cip_base_env_cov #(.CFG_T(uart_env_cfg));
`uvm_component_utils(uart_env_cov)

import uart_reg_pkg::RxFifoDepth;
import uart_reg_pkg::TxFifoDepth;

covergroup rx_fifo_level_cg with function sample(int lvl, bit rst);
cp_lvl: coverpoint lvl {
bins all_levels[] = {[0:RxFifoDepth]};
bins all_levels[] = {[0:uart_reg_pkg::RxFifoDepth]};
}
cp_rst: coverpoint rst;
cross cp_lvl, cp_rst;
endgroup

covergroup tx_fifo_level_cg with function sample(int lvl, bit rst);
cp_lvl: coverpoint lvl {
bins all_levels[] = {[0:TxFifoDepth]};
bins all_levels[] = {[0:uart_reg_pkg::TxFifoDepth]};
}
cp_rst: coverpoint rst;
cross cp_lvl, cp_rst;
Expand Down
21 changes: 18 additions & 3 deletions hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,6 @@ class reset_class;

parameter int IterationsPerDelta = 16;

import uvm_pkg::*;

typedef enum int {
OrderChildLags,
OrderChildLeads
Expand Down Expand Up @@ -101,6 +99,7 @@ class reset_class;
endfunction

task set_child_period(child_clk_e child_clk);
import uvm_pkg::*;
if (child_clk == ChildClkFaster) begin
`uvm_info(`gfn, $sformatf(
"Setting child clk (%0d ps) faster than reference (%0d ps)",
Expand All @@ -119,6 +118,7 @@ class reset_class;
endtask

task apply_resets();
import uvm_pkg::*;
`uvm_info(`gfn, "Start apply_resets", UVM_MEDIUM)
fork
clk_rst_vif.apply_reset(.reset_width_clks(cycles_reset_width));
Expand All @@ -139,27 +139,31 @@ class reset_class;
endtask

task set_quiescent();
import uvm_pkg::*;
`uvm_info(`gfn, "Setting quiescent inputs", UVM_MEDIUM)
reset_vif.parent_rst_ni = 1'b1;
reset_vif.sw_rst_req_i = 1'b0;
reset_vif.child_rst_ni = 1'b1;
endtask

task set_parent_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.parent_rst_ni == value) return;
`uvm_info(`gfn, $sformatf("Setting parent_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
reset_vif.parent_rst_ni = value;
endtask

task set_sw_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.sw_rst_req_i == value) return;
`uvm_info(`gfn, $sformatf("Setting sw_rst_req_i=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
reset_vif.sw_rst_req_i = value;
endtask

task set_child_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.child_rst_ni == value) return;
`uvm_info(`gfn, $sformatf("Setting child_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
Expand All @@ -184,6 +188,8 @@ class reset_class;

// Run a number of reset scenarios with some given cycle delays to allow CDC cycle fluctuations.
task run_iterations(input string description, input int delta_cycles, output int error_count);
import uvm_pkg::*;

error_count = 0;
for (int i = 0; i < IterationsPerDelta; ++i) begin
set_quiescent();
Expand All @@ -208,6 +214,8 @@ class reset_class;

// Run a parent reset to child reset.
task scan_parent_rst();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning parent resets", UVM_LOW)
sw_reset = 0;
parent_rst_n = 0;
Expand Down Expand Up @@ -237,6 +245,8 @@ class reset_class;
endtask

task scan_parent_release();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning parent release", UVM_LOW)
sw_reset = 0;
parent_rst_n = 0;
Expand Down Expand Up @@ -265,6 +275,8 @@ class reset_class;
endtask

task scan_sw_rst();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning sw resets", UVM_LOW)
sw_reset = 1;
parent_rst_n = 1;
Expand All @@ -288,6 +300,8 @@ class reset_class;
endtask

task scan_sw_release();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning sw releases", UVM_LOW)
sw_reset = 1;
parent_rst_n = 1;
Expand Down Expand Up @@ -330,6 +344,8 @@ class reset_class;
endtask

task body();
import uvm_pkg::*;

foreach (sec_cm_pkg::sec_cm_if_proxy_q[i]) begin
`uvm_info(`gfn, $sformatf("Path of proxy: %0s", sec_cm_pkg::sec_cm_if_proxy_q[i].path),
UVM_MEDIUM)
Expand Down Expand Up @@ -395,7 +411,6 @@ class reset_class;
endclass

module tb;

import uvm_pkg::*;

reset_class reset_cl;
Expand Down
21 changes: 18 additions & 3 deletions hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,6 @@ class reset_class;

parameter int IterationsPerDelta = 16;

import uvm_pkg::*;

typedef enum int {
OrderChildLags,
OrderChildLeads
Expand Down Expand Up @@ -101,6 +99,7 @@ class reset_class;
endfunction

task set_child_period(child_clk_e child_clk);
import uvm_pkg::*;
if (child_clk == ChildClkFaster) begin
`uvm_info(`gfn, $sformatf(
"Setting child clk (%0d ps) faster than reference (%0d ps)",
Expand All @@ -119,6 +118,7 @@ class reset_class;
endtask

task apply_resets();
import uvm_pkg::*;
`uvm_info(`gfn, "Start apply_resets", UVM_MEDIUM)
fork
clk_rst_vif.apply_reset(.reset_width_clks(cycles_reset_width));
Expand All @@ -139,27 +139,31 @@ class reset_class;
endtask

task set_quiescent();
import uvm_pkg::*;
`uvm_info(`gfn, "Setting quiescent inputs", UVM_MEDIUM)
reset_vif.parent_rst_ni = 1'b1;
reset_vif.sw_rst_req_i = 1'b0;
reset_vif.child_rst_ni = 1'b1;
endtask

task set_parent_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.parent_rst_ni == value) return;
`uvm_info(`gfn, $sformatf("Setting parent_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
reset_vif.parent_rst_ni = value;
endtask

task set_sw_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.sw_rst_req_i == value) return;
`uvm_info(`gfn, $sformatf("Setting sw_rst_req_i=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
reset_vif.sw_rst_req_i = value;
endtask

task set_child_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.child_rst_ni == value) return;
`uvm_info(`gfn, $sformatf("Setting child_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
Expand All @@ -184,6 +188,8 @@ class reset_class;

// Run a number of reset scenarios with some given cycle delays to allow CDC cycle fluctuations.
task run_iterations(input string description, input int delta_cycles, output int error_count);
import uvm_pkg::*;

error_count = 0;
for (int i = 0; i < IterationsPerDelta; ++i) begin
set_quiescent();
Expand All @@ -208,6 +214,8 @@ class reset_class;

// Run a parent reset to child reset.
task scan_parent_rst();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning parent resets", UVM_LOW)
sw_reset = 0;
parent_rst_n = 0;
Expand Down Expand Up @@ -237,6 +245,8 @@ class reset_class;
endtask

task scan_parent_release();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning parent release", UVM_LOW)
sw_reset = 0;
parent_rst_n = 0;
Expand Down Expand Up @@ -265,6 +275,8 @@ class reset_class;
endtask

task scan_sw_rst();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning sw resets", UVM_LOW)
sw_reset = 1;
parent_rst_n = 1;
Expand All @@ -288,6 +300,8 @@ class reset_class;
endtask

task scan_sw_release();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning sw releases", UVM_LOW)
sw_reset = 1;
parent_rst_n = 1;
Expand Down Expand Up @@ -330,6 +344,8 @@ class reset_class;
endtask

task body();
import uvm_pkg::*;

foreach (sec_cm_pkg::sec_cm_if_proxy_q[i]) begin
`uvm_info(`gfn, $sformatf("Path of proxy: %0s", sec_cm_pkg::sec_cm_if_proxy_q[i].path),
UVM_MEDIUM)
Expand Down Expand Up @@ -395,7 +411,6 @@ class reset_class;
endclass

module tb;

import uvm_pkg::*;

reset_class reset_cl;
Expand Down
21 changes: 18 additions & 3 deletions hw/top_earlgrey/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,6 @@ class reset_class;

parameter int IterationsPerDelta = 16;

import uvm_pkg::*;

typedef enum int {
OrderChildLags,
OrderChildLeads
Expand Down Expand Up @@ -101,6 +99,7 @@ class reset_class;
endfunction

task set_child_period(child_clk_e child_clk);
import uvm_pkg::*;
if (child_clk == ChildClkFaster) begin
`uvm_info(`gfn, $sformatf(
"Setting child clk (%0d ps) faster than reference (%0d ps)",
Expand All @@ -119,6 +118,7 @@ class reset_class;
endtask

task apply_resets();
import uvm_pkg::*;
`uvm_info(`gfn, "Start apply_resets", UVM_MEDIUM)
fork
clk_rst_vif.apply_reset(.reset_width_clks(cycles_reset_width));
Expand All @@ -139,27 +139,31 @@ class reset_class;
endtask

task set_quiescent();
import uvm_pkg::*;
`uvm_info(`gfn, "Setting quiescent inputs", UVM_MEDIUM)
reset_vif.parent_rst_ni = 1'b1;
reset_vif.sw_rst_req_i = 1'b0;
reset_vif.child_rst_ni = 1'b1;
endtask

task set_parent_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.parent_rst_ni == value) return;
`uvm_info(`gfn, $sformatf("Setting parent_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
reset_vif.parent_rst_ni = value;
endtask

task set_sw_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.sw_rst_req_i == value) return;
`uvm_info(`gfn, $sformatf("Setting sw_rst_req_i=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
reset_vif.sw_rst_req_i = value;
endtask

task set_child_reset(logic value, int cycles);
import uvm_pkg::*;
if (reset_vif.child_rst_ni == value) return;
`uvm_info(`gfn, $sformatf("Setting child_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH)
clk_rst_vif.wait_clks(cycles);
Expand All @@ -184,6 +188,8 @@ class reset_class;

// Run a number of reset scenarios with some given cycle delays to allow CDC cycle fluctuations.
task run_iterations(input string description, input int delta_cycles, output int error_count);
import uvm_pkg::*;

error_count = 0;
for (int i = 0; i < IterationsPerDelta; ++i) begin
set_quiescent();
Expand All @@ -208,6 +214,8 @@ class reset_class;

// Run a parent reset to child reset.
task scan_parent_rst();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning parent resets", UVM_LOW)
sw_reset = 0;
parent_rst_n = 0;
Expand Down Expand Up @@ -237,6 +245,8 @@ class reset_class;
endtask

task scan_parent_release();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning parent release", UVM_LOW)
sw_reset = 0;
parent_rst_n = 0;
Expand Down Expand Up @@ -265,6 +275,8 @@ class reset_class;
endtask

task scan_sw_rst();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning sw resets", UVM_LOW)
sw_reset = 1;
parent_rst_n = 1;
Expand All @@ -288,6 +300,8 @@ class reset_class;
endtask

task scan_sw_release();
import uvm_pkg::*;

`uvm_info(`gfn, "scanning sw releases", UVM_LOW)
sw_reset = 1;
parent_rst_n = 1;
Expand Down Expand Up @@ -330,6 +344,8 @@ class reset_class;
endtask

task body();
import uvm_pkg::*;

foreach (sec_cm_pkg::sec_cm_if_proxy_q[i]) begin
`uvm_info(`gfn, $sformatf("Path of proxy: %0s", sec_cm_pkg::sec_cm_if_proxy_q[i].path),
UVM_MEDIUM)
Expand Down Expand Up @@ -395,7 +411,6 @@ class reset_class;
endclass

module tb;

import uvm_pkg::*;

reset_class reset_cl;
Expand Down
Loading
Loading