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openvizsla edited this page Mar 14, 2014 · 1 revision

OpenVizsla was designed to be a flexible, open hardware design that would allow a rich set of third-party programs to control it and interpret the outputs. However, third parties cannot develop software without hardware to test, but we cannot make working hardware without some software to test it. Therefore, simple hardware-testing software was written to exercise all features of the hardware, so that the hardware could successfully be made. All of these limitations can be overcome with improved software.

Known issues:

  • Host code does not currently build on Windows (need to add support for building a libov.dll, and need clear instructions on installing the appropriate libusb and python runtimes)
  • Buffering via SDRAM is not currently implemented in master (an earlier PoC exists in git)
  • User must explicitly specify the sniffing speed on the command line; it should be possible to auto detect this
  • LEDs and switch do not do anything
  • Resyncing the FPGA input stream does not always work well (i.e. if you ^C ovctl during a sniff, you will get some garbage when you rerun it)
  • Sniffing at HS pegs the CPU at 100%; the Python code needs to be profiled and inner loops may need to be optimized or reimplemented in C. (This was partially attempted with usb_interp.c vs usb_interp.py, but it did not solve the problem.)
  • You must explicitly provide the path to ov3.fwpkg upon each invocation of ovctl.py
  • Wireshark support is extremely primitive
  • vusb-analyzer support is not yet implemented
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