ov3 errata

10 ov3 PCBs were made, 5 are being hand-assembled.

1. L1 is wrong in the schematic and on the board; it is 2.2uH, and should be 4.7uH or 10uF per the datasheet. (fixed in OV3.1)
2. The wrong capacitors were ordered for the 10uF ceramic caps (ordered 0.01uF caps!). (Fix: 10uF tantalum caps were substituted for the power supply (since this is critical), and 4.7uF ceramic caps were substituted for the 10uF bulk decoupling capacitors.)
3. DONE is missing a 330-ohm pullup. (Fix: Added R18 to OV3.1, and soldered a resistor onto ov3 boards.)
4. PROG is missing a 10K pullup. (Fix: Added R19 to OV3.1, and soldered a resistor onto ov3 boards.)
5. INIT_B is missing a 10K pullup. (Fix: Added R20 to OV3.1, and soldered a resistor onto ov3 boards.)
6. HSWAPEN (RAM_RAS_B) is missing a 10K pulldown. (Fix: Added R21 to OV3.1 … it's not clear whether this is actually necessary or just good practice.)
7. CCLK might need termination. (Fix: Added 33-ohm resistor R22 to OV3.1)
8. CLKOUT might need termination. (Fix: Added 33-ohm resistor R23 to OV3.1)
9. L1 is difficult to solder with an iron; the pads could be made a bit bigger.
10. U4 (the ULPI PHY) is difficult to hand-solder, but there is probably nothing to be done about it
11. C8 and C9 have spurious "10u" marking on the PCB (they should really be 4.7uF) (fixed in OV3.1)
12. 3 vias are untented on the top layer (fixed in OV3.1)
13. The serial number space on the silkscreen is too short to fit a serial number sticker. (fixed in OV3.1)
14. The JTAG is wired up incorrectly in the schematic; the FPGA signals TDI, TDO, and TCK are rotated by one. (fixed in OV3.1)
15. Y1 (the 26MHz ULPI PHY) needs a 1MOhm resistor soldered in parallel to it for the oscillator to work. (fixed in OV3.1)
16. ACBUS4 (AKA SIWUA) on the FTDI should be pulled up to +3.3v and/or connected to the FPGA (perhaps via TP15). (fixed in OV3.1)
17. Add +5v and +1.2v to spare I/O header P4 (fixed in OV3.1)
18. Space out LEDs and make LED1-LED3 red, yellow, green to make it easier to distinguish them (fixed in OV3.1)
19. Add optional SMA triggering input and output jacks "(trig in, 50 ohm par term to GND, trig-out direct to GPIO)" (fixed in ov3.1)

OV3.1 errata

1. Due to a layout error, the +5v rail is disconnected from the input of the +1.2v switching supply. Workaround: Jumper from the left side of C10 to the +5v testpoint.
2. Due to a layout error, the +1.2v testpoint is not connected to anything. Workaround: Probe the +1.2v rail at the left side of C1 or the top side of L1, if necessary.
3. INIT_B is getting pulled down to +1.08v after FPGA configuration, because OV3.1 uses a weaker pull-up than OV3 (10K vs 4.3K). This makes ovctl.py think that there was a CRC error uploading the bitstream to the FPGA. Fix: bitstream fixed in git commit 62ae40c3 to disable default pull-down on INIT_B
4. Bottom silkscreen labels for P4 no longer match the labels on the top silkscreen.
5. R3 silkscreen should say 100 (ohms)