Update implementation of SRA

physical-computation · May 17, 2022 · 215ac69 · 215ac69
1 parent 97ec401
commit 215ac69
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/verilog/alu.v b/verilog/alu.v
@@ -110,7 +110,7 @@ module alu(ALUctl, A, B, ALUOut, Branch_Enable);
 			/*
 			 *	SRA (the fields also matches the other SRA variants)
 			 */
-			`kSAIL_MICROARCHITECTURE_ALUCTL_3to0_SRA:	ALUOut = A >>> B[4:0];
+			`kSAIL_MICROARCHITECTURE_ALUCTL_3to0_SRA:	ALUOut = $signed(A) >>> B[4:0];
 
 			/*
 			 *	SLL (the fields also match the other SLL variants)