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Update package with dequantization parameters
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@belanoa
belanoa committed Jan 22, 2025
1 parent fa7c2cd commit 6dea8de
Showing 1 changed file with 47 additions and 6 deletions.
53 changes: 47 additions & 6 deletions rtl/redmule_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,12 +11,12 @@ import hwpe_stream_package::*;

package redmule_pkg;

parameter int unsigned DATA_W = 288; // TCDM port dimension (in bits)
parameter int unsigned DATA_W = 256 + 32; // TCDM port dimension (in bits)
parameter int unsigned MemDw = 32;
parameter int unsigned NumByte = MemDw/8;
parameter int unsigned ADDR_W = hci_package::DEFAULT_AW;
parameter int unsigned DATAW = DATA_W - MemDw;
parameter int unsigned REDMULE_REGS = 18;
parameter int unsigned REDMULE_REGS = 22;
parameter int unsigned N_CONTEXT = 2;
parameter fpnew_pkg::fp_format_e FPFORMAT = fpnew_pkg::FP16;
parameter int unsigned BITW = fpnew_pkg::fp_width(FPFORMAT);
Expand All @@ -32,6 +32,13 @@ package redmule_pkg;
parameter int unsigned MIN_FMT = fpnew_pkg::min_fp_width(FpFmtConfig);
parameter int unsigned DW_CUT = DATA_W - ARRAY_HEIGHT*(PIPE_REGS + 1)*MIN_FMT;


//Quantization parameters
parameter logic DEQUANT_EN = 1; //This enables support for 2, 4, and 8-bit quantization
parameter logic DEQUANT_INT3_EN = 0; //Enable support for INT3 quantized weights (currently unsupported)

parameter int unsigned GROUP_ID_WIDTH = 16;

// Register File mapping
/**********************
** Slave RF indexing **
Expand All @@ -42,9 +49,15 @@ package redmule_pkg;
parameter int unsigned MCFIG0 = 3; // 0x0C --> [31:16] -> K size, [15: 0] -> M size
parameter int unsigned MCFIG1 = 4; // 0x10 --> [31: 0] -> N Size
// Matrix arithmetic config register
// [18:17] -> Quantized format
// [16] -> Dequantization enable
// [12:10] -> Operation selection
// [ 9: 7] -> Input/Output format
parameter int unsigned MACFG = 5; // 0x14
// Dequantization config registers
parameter int unsigned GIDX_ADDR_R = 6; // 0x18
parameter int unsigned SCALES_ADDR_R = 7; // 0x1C
parameter int unsigned ZEROS_ADDR_R = 8; // 0x20
/**********************
** Final RF indexing **
**********************/
Expand Down Expand Up @@ -82,6 +95,13 @@ package redmule_pkg;
// [12:10] -> computing format
// [0:0] -> GEMM selection
parameter int unsigned OP_SELECTION = 17; // 0x44
// One register is used for the dequantization parameters
// [2:1] -> Quantized format
// [0:0] -> Dequantization enable
parameter int unsigned DEQUANT_MODE = 18; // 0x48
parameter int unsigned GIDX_ADDR = 19; // 0x4C

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[verible-verilog-lint] rtl/redmule_pkg.sv#L102 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"rtl/redmule_pkg.sv"  range:{start:{line:102  column:52}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:102  column:52}  end:{line:103}}  text:"  parameter int unsigned GIDX_ADDR    = 19; // 0x4C\n"}
parameter int unsigned SCALES_ADDR = 20; // 0x50
parameter int unsigned ZEROS_ADDR = 21; // 0x54

parameter bit[6:0] MCNFIG = 7'b0001011; // 0x0B
parameter bit[6:0] MARITH = 7'b0101011; // 0x2B
Expand All @@ -101,10 +121,13 @@ package redmule_pkg;
CSR_REDMULE_MACFG = 12'h805
} redmule_csr_num_e;

parameter int unsigned NumStreamSources = 3; // X, W, Y
parameter int unsigned XsourceStreamId = 0;
parameter int unsigned WsourceStreamId = 1;
parameter int unsigned YsourceStreamId = 2;
parameter int unsigned NumStreamSources = 6; // X, W/scales, Y, gidx, wq, zeros
parameter int unsigned XsourceStreamId = 0;
parameter int unsigned WsourceStreamId = 1;
parameter int unsigned YsourceStreamId = 2;
parameter int unsigned GIdxsourceStreamId = 3;
parameter int unsigned WQsourceStreamId = 4;
parameter int unsigned ZerossourceStreamId = 5;

typedef enum logic { LD_IN_FMP, LD_WEIGHT } source_sel_e;
typedef enum logic { LOAD, STORE } ld_st_sel_e;
Expand All @@ -114,6 +137,9 @@ package redmule_pkg;
hci_package::hci_streamer_ctrl_t w_stream_source_ctrl;
hci_package::hci_streamer_ctrl_t y_stream_source_ctrl;
hci_package::hci_streamer_ctrl_t z_stream_sink_ctrl;
hci_package::hci_streamer_ctrl_t gid_stream_source_ctrl;
hci_package::hci_streamer_ctrl_t wq_stream_source_ctrl;
hci_package::hci_streamer_ctrl_t zeros_stream_source_ctrl;
fpnew_pkg::fp_format_e input_cast_src_fmt;
fpnew_pkg::fp_format_e input_cast_dst_fmt;
fpnew_pkg::fp_format_e output_cast_src_fmt;
Expand All @@ -125,16 +151,24 @@ package redmule_pkg;
hci_package::hci_streamer_flags_t w_stream_source_flags;
hci_package::hci_streamer_flags_t y_stream_source_flags;
hci_package::hci_streamer_flags_t z_stream_sink_flags;
hci_package::hci_streamer_flags_t gid_stream_source_flags;
hci_package::hci_streamer_flags_t wq_stream_source_flags;
hci_package::hci_streamer_flags_t zeros_stream_source_flags;
} flgs_streamer_t;

typedef enum logic [1:0] { QINT_2=2'h0, QINT_4=2'h1, QINT_8=2'h2, QINT_3=2'h3 } qint_fmt_e;

typedef struct packed {
logic d_shift;
logic h_shift;
logic blck_shift;
logic load;
logic pad_setup;
logic [$clog2(TOT_DEPTH):0] cols_lftovr;
logic [$clog2(ARRAY_WIDTH):0] rows_lftovr;
logic [$clog2(DEPTH)-1:0] slots;
logic dequant;
qint_fmt_e q_int_fmt;
} x_buffer_ctrl_t;

typedef struct packed {
Expand All @@ -147,6 +181,8 @@ package redmule_pkg;
logic load;
logic [$clog2(TOT_DEPTH):0] cols_lftovr;
logic [$clog2(ARRAY_HEIGHT):0] rows_lftovr;
logic dequant;
qint_fmt_e q_int_fmt;
} w_buffer_ctrl_t;

typedef struct packed {
Expand Down Expand Up @@ -229,6 +265,9 @@ package redmule_pkg;
logic [31:0] x_addr;
logic [31:0] w_addr;
logic [31:0] z_addr;
logic [31:0] gidx_addr;
logic [31:0] scales_addr;
logic [31:0] zeros_addr;
logic [15:0] m_size;
logic [15:0] n_size;
logic [15:0] k_size;
Expand Down Expand Up @@ -262,6 +301,8 @@ package redmule_pkg;
fpu_fmt_e input_format;
fpu_fmt_e computing_format;
logic gemm_selection;
logic dequant_enable;
qint_fmt_e q_int_fmt;
} redmule_config_t;

typedef enum {
Expand Down

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