Skip to content

Issues: riscv/riscv-isa-manual

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

211 Open 720 Closed
211 Open 720 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Notation for branch/jump target ranges might be misleading
#1781 opened Dec 19, 2024 by WorldofJARcraft
Does a software-injected interrupt get affected by the xideleg register
#1775 opened Dec 15, 2024 by tom-guo-sudo
4
Clarification about access to a physical address which is higher than the maximal supported physical address
#1774 opened Dec 14, 2024 by leBsky
1
Integrate Load/Store Pair for RV32
#1766 opened Dec 11, 2024 by christian-herber-nxp
1
HUPMM introduced by Ssnpm not updated in layout of hstatus
#1763 opened Dec 10, 2024 by viktoryou
mcause/scause values when H is implemented
#1762 opened Dec 10, 2024 by pdonahue-ventana
Should it raise an exception when VA exceed the max range of the VA when mmu off? what kind of the that exception?
#1754 opened Dec 6, 2024 by rock-ifly
3
How to understand the "convert an invalid address into some other invalid address" in 3.1.14 MEPC register description
#1753 opened Dec 3, 2024 by rock-ifly
3
Seed CSR missing from CSR listings
#1747 opened Nov 29, 2024 by Timmmm
1
Does riscv allow vector load/store access the same device address multiple times?
#1741 opened Nov 25, 2024 by AlexGJL
3
instret, cycle, time outside of Zicntr (and hpmpcounterN outside Zihpm)
#1734 opened Nov 22, 2024 by dhower-qc
10
Specify what imprecise traps are
#1728 opened Nov 15, 2024 by Timmmm
11
Conflicting exception types caused by misaligned AMO instructions.
#1726 opened Nov 15, 2024 by jillleon007
8
Bus-error clarification
#1725 opened Nov 14, 2024 by oolegoon
2
How to decide the memory attribute when PBMT=NC & PMA=IO ?
#1723 opened Nov 13, 2024 by rock-ifly
1
How to understand this sentence in the PM spec--"Alternatively, an implementation may choose to "waste" TLB capacity by having up to 4 duplicate entries for each page."
#1721 opened Nov 11, 2024 by chara811
1
When PMLEN=16 and hgatp=sv48x4, Is GPA[49:48] =2b00?
#1720 opened Nov 11, 2024 by chara811
1
Sail Manual link is 404
#1718 opened Nov 8, 2024 by ha0lyu
1
Reason for vstart≥vl requiring undisturbed tail elements even with ta vtype
#1715 opened Nov 7, 2024 by dzaima
1
Specify misa.M behaviour with Zmmul
#1711 opened Nov 5, 2024 by Timmmm
3
"In a two-stage address translation, is it possible to configure VSatp as sv39 and hgatp as sv48, or VSatp as sv48 and hgatp as sv39?
#1703 opened Oct 31, 2024 by chara811
1
When the PM feature is enabled, can PMLEN be set to 7 in sv48 mode?
#1702 opened Oct 30, 2024 by chara811
4
Please extend the explanation on slideup/slidedown
#1701 opened Oct 29, 2024 by lu-zero
What are the sources of memory attributes under different translation mechanisms?
#1699 opened Oct 28, 2024 by chara811
4
why are the hstatus.VTSR/VTVM and VTW permission check different?
#1695 opened Oct 23, 2024 by yinhanquan
ProTip! Follow long discussions with comments:>50.