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Pull requests: riscv/riscv-isa-manual

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Pull requests list

Fix the Missing Vector CSR in listing table
#1698 opened Oct 26, 2024 by MrVyM Loading…
Fix list of vector crypto extensions that require SEW=64
#1697 opened Oct 25, 2024 by ebiggers Loading…
1
Improve table: Compressed instruction formats
#1696 opened Oct 24, 2024 by cousteaulecommandant Loading…
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL
#1653 opened Sep 26, 2024 by nibrunieAtSi5 Loading…
17
Add Smctr/Sscctr
#1615 opened Aug 28, 2024 by bcstrongx Loading…
6
Release the constraint to enable e8mf8 in EEW=32
#1613 opened Aug 24, 2024 by sequencer Loading…
3
Makefile changes to include Highlighter Sail
#1608 opened Aug 22, 2024 by AlfredoRodrigues4 Loading…
10
Added Instruction Description
#1603 opened Aug 16, 2024 by AFOliveira Loading…
14
Specify the interaction between CSRRS/C and "reads as" bits
#1581 opened Aug 6, 2024 by Timmmm Loading…
2
Clarify interaction of CBOs and PBMTs
#1570 opened Jul 26, 2024 by Timmmm Loading…
Add draft of Svukte extension
#1564 opened Jul 25, 2024 by aswaterman Loading…
39
Clarify that misaligned atomicity granule PMA applies to the compress…
#1557 opened Jul 24, 2024 by romanheros Loading…
Define format of memory-mapped msip register Privileged Architecture v1.14
#1541 opened Jul 17, 2024 by aswaterman Loading…
2
Update PMP spec to use "memory operation"
#1434 opened May 29, 2024 by Timmmm Loading…
9
Clarify CBO for unaligned rs1
#1433 opened May 29, 2024 by Timmmm Loading…
1
15
[AdditionalVectorCrypto] adding section on addition vector crypto extensions
#1306 opened Mar 28, 2024 by nibrunieAtSi5 • Draft
8 of 13 tasks
37
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