Cheshire (CVA6) support #129
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This PR adds build support for the Cheshire RISCV64 SoC. This system requires that huge page tests and the timer tests be disabled as the RAM is too small on the target FPGA (Digilent Genesys 2) and there are no hardware timers in Cheshire respectively. This PR requires the following PRs to merge before it can be used standalone:
seL4/seL4#1354
seL4/util_libs#188