Merge pull request #1226 from slaclab/pre-release

Release Candidate v2.54.0
slaclab · Jan 24, 2025 · 18a3556 · 18a3556
2 parents 60065b6 + 04dcaa2
commit 18a3556
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Showing 59 changed files with 1,943 additions and 35 deletions.
diff --git a/LICENSE.txt b/LICENSE.txt
@@ -1,5 +1,5 @@
 
-Copyright (c) 2024, The Board of Trustees of the Leland Stanford Junior 
+Copyright (c) 2025, The Board of Trustees of the Leland Stanford Junior 
 University, through SLAC National Accelerator Laboratory (subject to receipt 
 of any required approvals from the U.S. Dept. of Energy). All rights reserved. 
 Redistribution and use in source and binary forms, with or without 

diff --git a/axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd b/axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd
@@ -443,7 +443,7 @@ begin
                v.wMaster.wdata(23 downto 16)   := r.lastUser;
                v.wMaster.wdata(15 downto 4)    := (others => '0');
                v.wMaster.wdata(3)              := r.continue;
-               v.wMaster.wdata(2)              := '0';
+               v.wMaster.wdata(2)              := r.dmaWrTrack.overflow;
                v.wMaster.wdata(1 downto 0)     := r.result;
 
                v.wMaster.wstrb := resize(x"FF", 128);

diff --git a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd
@@ -77,6 +77,7 @@ entity GigEthGtyUltraScaleWrapper is
       gtRefClk            : in  sl                                             := '0';
       gtClkP              : in  sl                                             := '1';
       gtClkN              : in  sl                                             := '0';
+      gtClkOut            : out sl;
       -- Copy of internal MMCM reference clock and Reset
       refClkOut           : out sl;
       refRstOut           : out sl;
@@ -122,7 +123,7 @@ begin
          IB    => gtClkN,
          CEB   => '0',
          ODIV2 => gtClk,
-         O     => open);
+         O     => gtClkOut);
 
    BUFG_GT_Inst : BUFG_GT
       port map (

diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd
@@ -70,6 +70,7 @@ entity XauiGtyUltraScaleWrapper is
       -- MGT Clock Port (156.25MHz or 312.5MHz)
       gtClkP             : in  sl;
       gtClkN             : in  sl;
+      gtClkOut           : out  sl;
       -- MGT Ports
       gtTxP              : out slv(3 downto 0);
       gtTxN              : out slv(3 downto 0);
@@ -88,6 +89,7 @@ architecture mapping of XauiGtyUltraScaleWrapper is
 begin
 
    phyReady <= linkUp;
+   gtClkOut <= refClk;
 
    U_refClk : IBUFDS_GTE4
       port map (