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    • C
      Other
      1084245Updated Dec 24, 2024Dec 24, 2024
    • This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
      Makefile
      Creative Commons Attribution 4.0 International
      1211Updated Dec 23, 2024Dec 23, 2024
    • A base container image populated with the dependencies to build the RISC-V Documentation.
      Apache License 2.0
      81004Updated Dec 23, 2024Dec 23, 2024
    • RISC-V Opcodes
      Python
      BSD 3-Clause "New" or "Revised" License
      3057052725Updated Dec 20, 2024Dec 20, 2024
    • RISC-V Instruction Set Manual
      TeX
      Creative Commons Attribution 4.0 International
      6523.8k21116Updated Dec 20, 2024Dec 20, 2024
    • This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      Python
      Creative Commons Attribution 4.0 International
      3258397Updated Dec 20, 2024Dec 20, 2024
    • learn

      Public
      Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
      Creative Commons Zero v1.0 Universal
      7662710Updated Dec 20, 2024Dec 20, 2024
    • Sail RISC-V model
      Coq
      Other
      1714868963Updated Dec 19, 2024Dec 19, 2024
    • docs-spec-template

      Public template
      Makefile
      Creative Commons Attribution 4.0 International
      212432Updated Dec 18, 2024Dec 18, 2024
    • The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.
      Makefile
      Creative Commons Attribution 4.0 International
      2101Updated Dec 18, 2024Dec 18, 2024
    • Makefile
      65100Updated Dec 18, 2024Dec 18, 2024
    • riscv-b

      Public
      "B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions
      Makefile
      Creative Commons Attribution 4.0 International
      4500Updated Dec 18, 2024Dec 18, 2024
    • Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      Creative Commons Attribution 4.0 International
      50254414Updated Dec 18, 2024Dec 18, 2024
    • Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
      Makefile
      Creative Commons Attribution 4.0 International
      4200Updated Dec 18, 2024Dec 18, 2024
    • This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
      Makefile
      Creative Commons Attribution 4.0 International
      184320Updated Dec 18, 2024Dec 18, 2024
    • The Zabha extension provides support for byte and halfword atomic memory operations.
      Makefile
      Creative Commons Attribution 4.0 International
      8800Updated Dec 18, 2024Dec 18, 2024
    • Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      Creative Commons Attribution 4.0 International
      4701Updated Dec 18, 2024Dec 18, 2024
    • Documentation developer guide
      TeX
      Creative Commons Attribution 4.0 International
      349542Updated Dec 18, 2024Dec 18, 2024
    • riscv-cfi

      Public
      This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
      Makefile
      Creative Commons Attribution 4.0 International
      228600Updated Dec 18, 2024Dec 18, 2024
    • GitHub repository for the Functional Safety SIG Whitepaper Development
      TeX
      Creative Commons Attribution 4.0 International
      1101Updated Dec 18, 2024Dec 18, 2024
    • The ISA specification for the Zalasr extension.
      Makefile
      Creative Commons Attribution 4.0 International
      2231Updated Dec 18, 2024Dec 18, 2024
    • This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
      Makefile
      Creative Commons Attribution 4.0 International
      51712Updated Dec 17, 2024Dec 17, 2024
    • RISC-V Performance Events Specification
      Python
      Creative Commons Attribution 4.0 International
      3452Updated Dec 17, 2024Dec 17, 2024
    • CSS
      Creative Commons Attribution 4.0 International
      163220Updated Dec 17, 2024Dec 17, 2024
    • RISC-V Architecture Profiles
      Makefile
      Creative Commons Attribution 4.0 International
      35126102Updated Dec 16, 2024Dec 16, 2024
    • Working Draft of the RISC-V Debug Specification Standard
      Python
      Other
      93466578Updated Dec 10, 2024Dec 10, 2024
    • Dot-Product Extension
      Makefile
      Creative Commons Attribution 4.0 International
      4433Updated Dec 10, 2024Dec 10, 2024
    • OpenEmbedded/Yocto layer for RISC-V Architecture
      BitBake
      Other
      143371172Updated Dec 4, 2024Dec 4, 2024
    • This repository holds the front matter pages for the RISC-V Library
      1100Updated Dec 3, 2024Dec 3, 2024
    • Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
      Makefile
      Creative Commons Attribution 4.0 International
      3861Updated Dec 2, 2024Dec 2, 2024