Updating with latest textual changes

src/zilsd.adoc

@@ -39,9 +39,18 @@ Even if naturally aligned, the memory access might not be performed atomically.
 
 If the effective address is a multiple of 4, then each word access is required to be performed atomically.
 
-To ensure fault handling is possible for the load instructions, it must be ensured that the register which is the source of the base address is not overwritten before the entire operation is complete.
+The following table summarizes the required behavior:
+
+[%header]
+|===
+|Alignment |Word accesses guaranteed atomic? |Can cause misaligned trap?
+|8B |yes |no
+|4B not 8B |yes |yes
+|else |no | yes
+|===
+
+To ensure resumable trap handling is possible for the load instructions, the base register must have its original value if a trap is taken. The other register in the pair can have been updated.
 This affects x2 for the stack pointer relative instruction and rs1 otherwise.
-To guarantee this, if one of the destination registers of the pair is the source register containing the base, it must not be written to before the other register in the pair has been written.
 
 [NOTE]
 ====
@@ -89,9 +98,10 @@ Zclsd adds the following RV32-only instructions:
 
 === Use of x0 as operand
 
-LD instructions with destination `x0` are processed as any other load, but the result is discarded entirely. Specifically, a load pair to `x0` does not cause `x1` to be written. For C.LDSP, usage of `x0` as the destination is reserved.
+LD and C.LD instructions with destination `x0` are processed as any other load, but the result is discarded entirely and x1 is not written.
+For C.LDSP, usage of `x0` as the destination is reserved.
 
-When using `x0` as `src` of SD or C.SDSP, the entire 64-bit operand is zero — i.e., register `x1` is not accessed.
+When using `x0` as `src` of SD, C.SD or C.SDSP, the entire 64-bit operand is zero — i.e., register `x1` is not accessed.
 
 === Exception Handling