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Hardware Error exception priority #1223

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Feb 11, 2024
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Hardware Error exception priority #1223

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5 changes: 4 additions & 1 deletion src/machine.adoc
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Expand Up @@ -1847,7 +1847,10 @@ this context, "data" encompasses all types of information used within a RISC-V
hart. Upon a hardware error exception, the `__x__epc` register is set to the
address of the instruction that attempted to access corrupted data, while the
`__x__tval` register is set either to 0 or to the virtual address of an
instruction fetch, load, or store that attempted to access corrupted data.
instruction fetch, load, or store that attempted to access corrupted data. The
priority of Hardware Error exception is implementation-defined, but any given
occurrence is generally expected to be recognized at the point in the overall
priority order at which the hardware error is discovered.
====

==== Machine Trap Value Register (`mtval`)
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